As it is known, phase change non-volatile memories, so-called ePCMs (embedded Phase Change Memories), represent a new generation of integrated memories, in which, to store information, the characteristics of materials having the property of switching between phases having different electrical characteristics are exploited. For example, these materials can switch between an amorphous, disorderly, phase and a crystalline or polycrystalline, orderly, phase, and the two phases are associated to resistivities of considerably different value, and consequently to a different value of a datum stored. For example, the elements of the VI group of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), referred to as chalcogenides or chalcogenic materials, may advantageously be used for producing phase change memory cells; in particular, an alloy made up of germanium (Ge), antimony (Sb), and tellurium (Te), known as GST (having the chemical composition Ge2Sb2Te5) is currently widely used in such memory cells.
Phase changes may be obtained by locally increasing the temperature of the cells of chalcogenic material, through resistive electrodes (generally known as heaters) set in contact with respective regions of chalcogenic material.
Selection devices (for example, MOSFETs), are connected to the heaters and enable passage of a programming electric current through a respective heater; this electric current, by the Joule effect, generates the temperatures necessary for the phase change. In particular, when the chalcogenic material is in the amorphous state, at a high resistivity (the so-called RESET state), it is required to apply a current/voltage pulse (or an appropriate number of current/voltage pulses) of duration and amplitude such as to enable the chalcogenic material to cool slowly. Subjected to this treatment, the chalcogenic material changes its state and switches from the high-resistivity state to a low-resistivity state (the so-called SET state). Vice versa, when the chalcogenic material is in the SET state, it is required to apply a current/voltage pulse having appropriate duration and high amplitude so as to cause the chalcogenic material to return into the high-resistivity amorphous state.
During reading, the state of the chalcogenic material is detected by applying a voltage sufficiently low as not to cause a sensible heating thereof, and then by reading the value of the current flowing in the memory cell. Given that the current is proportional to the conductivity of the chalcogenic material, it is possible to determine in which state the material is, and consequently determine the datum stored in the memory cell.
In general, PCMB afford important advantages, among which are high scalability and reading speed combined with a reduced current consumption and a high efficiency.
In a known way, and as shown schematically in FIG. 1 (limited to just the parts required for an understanding of the present embodiments), a non-volatile PCM device 1 includes a memory array 2 made of a plurality of memory cells 3, arranged in rows (wordlines, WL) and columns (bitlines, BL). Each memory cell 3 includes a phase change storage element 3a and selector element 3b, which are connected in series between a respective bitline BL and a terminal at a reference potential (for example, ground, GND). In particular, a wordline WL is defined by the set of all the control terminals of the selector transistors aligned along one and the same row.
The storage element 3a includes a phase change material (for example, a chalcogenide, such as GST), and is consequently able to store data in the form of resistance levels associated to the different phases assumed by the phase change material. The selector element 3b, as in the embodiment illustrated, may be an NMOS transistor having its gate terminal connected to the wordline WL, its drain terminal connected to the storage element 3a, and its source terminal connected to the terminal at reference potential (in particular ground, GND). The selector element 3b is controlled so as to enable, when selected, the passage of a reading/programming driving current through the phase change storage element 3a, during respective reading/programming operations.
A column decoder 4 and a row decoder 5 enable selection, based on address signals received at the input and more or less complex decoding schemes, of the memory cells 3, and in particular of the corresponding wordlines WL and bitlines BL, each time addressed, enabling biasing thereof at appropriate voltage and current values by corresponding driving stages. In particular, shown in FIG. 1 is the driving stage 6 designed to supply the driving currents for the bitlines BL of the memory array 2 during the operations of programming of the SET or RESET states in the memory cells 3.
In particular, it is known that these programming operations, both when programming of the SET state and when programming of the RESET state of the chalcogenide material of the memory cells 3 is required, require supplying to the storage elements 3a of high value current pulses, for the activation of the mechanisms of a change of state. Moreover, an accurate control of the parameters of the programming current pulses may be important for ensuring efficient and repeatable transitions between the SET and RESET states, and this control has to be ensured in a wide range of values of current so as to deal with the various operating conditions of the memory device 1. For example, a low distortion of the waveform of the current pulses may be in a wide range between 100 μA and 1000 μA (with a maximum voltage generated on the bitlines BL by the column decoder 4 that may reach a value of approximately 3 V).
Once again by way of example, FIGS. 2a and 2b show plots of possible RESET pulses and SET pulses. FIG. 2a shows a reset pulse between 500 to 700 μA, having a duration of 200 ns. FIG. 2b shows a set pulse between 200 to 300 μA, having a deviation of 2000 ns. It is evident that meeting of the above mentioned stringent conditions in the control of the parameters of the waveforms of the programming current pulses may be an important aspect to be addressed in the design of memory devices and that may represent one of the major important aspects thereof.
FIG. 3 is a schematic illustration of a driving stage 6, of a known type, for supplying from a charge pump having a voltage Vcp, during the programming operations, output driving currents, here designated by I<k> (where k is an index of integer value, for example ranging between 0 and 31, in the case where the driving stage 6 is connected to thirty-two bitlines BL), designed for driving the memory cells 3. The output driving currents Ik are supplied to the column decoder 4, and are then to be provided, according to the decoding schemes implemented, to the bitlines BL of the memory array 2.
In detail, the driving stage 6 includes a driving-control unit 7, having a low-impedance input receiving an input current Iin of a low value (i.e., sensibly lower than the value required for the output driving currents Ik), for example, equal to 200 μA in the case where the value required for the output driving current Ik is 800 μA, generated by an input stage 8 as a function of the specific required memory operation (for example, having a different value for the SET and RESET programming operations). The input-current-generator stage 8 may be implemented in a wide range of ways, generally depending on the type of application. For example, a digital-to-analog converter (DAC) can be used, whereby a given output current corresponds to a given configuration of a certain number of input bits.
The driving stage 6 further comprises an output driving unit 9, connected to the driving-control unit 7 and designed to generate and distribute to the bitlines BL the output driving currents Ik. The driving-control unit 7 and the output driving unit 9 are moreover supplied by a charge-pump stage 10, which supplies suitable supply electrical quantities, in particular a boosted voltage Vcp in the high-voltage (HV) range (for example, in the range between 4 V and 5 V), of a value higher than the low logic voltages used in the memory device 1 (which have, for example, a value in the range between 1.08 V and 1.32 V).
The driving-control unit 7 includes a plurality of control sub-units 11, and the output driving unit 9 comprises a respective plurality of driving sub-units 12, each of which, appropriately supplied by the charge-pump stage 10, is designed to supply a respective output driving current Ik, having a value amplified by a factor β with respect to the input current Iin, according to the relation: Ik=Iin·β. The voltages supplied at output by the driving sub-units 12 are, for example, in the region of 3 V.
In particular, each control sub-unit 11 drives in an appropriate way a respective set of driving sub-units 12, supplying appropriate control signals for enabling supply at output of the respective output driving currents Ik. For example, each control sub-unit 11 may drive four respective driving sub-units 12 (so that in the driving stage eight control sub-units 11 may, for example, be present for supplying thirty-two output driving currents Ik via a corresponding number of driving sub-units 12).
As illustrated in FIG. 4 (which refers, for simplicity of illustration, to a single control sub-unit 11 and to the corresponding set of driving sub-units 12, in the example four in number), each control sub-unit 11 forms, with the corresponding set of driving sub-units 12, a current mirror in a cascode configuration, designed to mirror on the various outputs the input current Iin with amplification factor β. The control sub-unit 11 defines the input branch of the current mirror, while the driving sub-units 12 define respective output branches of the same mirror, connected to one another in parallel.
In greater detail, the control sub-unit 11 includes a cascode control transistor MCc and an input mirror transistor MPc, both of a PMOS type and connected in series between a first input In1 of the driving stage 6, which receives the input current Iin, and a second input In2 of the driving stage 6, connected to the output of the charge-pump stage 10 and receiving the boosted voltage Vcp. The control terminal of the cascode control transistor MCc is connected to a third input In3, which receives a cascode biasing voltage Vcascp, of an appropriate value, while the control terminal of the input mirror transistor MPc is connected to the first input In1 and to the respective conduction terminal of the cascade control transistor MCC, so as to provide the diode configuration for the current-mirroring operation.
Each driving sub-unit 12 (for convenience an n-th driving sub-unit 12 is described, but altogether similar considerations apply to the other sub-units of the corresponding set, designated by n+1, n+2 and n+3, where n is an integer index representing the set) comprises a respective cascode driving transistor MCn and an output mirror transistor MPn, both of a PMOS type and connected in series between the second input In2 and a respective output of the driving stage 6, supplying the respective output driving current, here designated by I<n>. The control terminals of the cascode driving transistor MCn and of the output mirror transistor MPn are connected to the control terminals of the cascode control transistor MCc and of the input mirror transistor MPc, respectively.
The circuit configuration described enables mirroring of the input current Iin with the desired amplification factor β, given by the different sizing ratios (width/length, W/L) of the transistors in the input and output branches. In particular, the cascode configuration advantageously enables a drain-to-source voltage drop Vds to be obtained on the output mirror transistors MPn that is substantially constant, so as to ensure a good repeatability of the electrical performance.
However, the configuration described also has some limitations that do not enable full exploitation of the advantages thereof.
In particular, for reason of speed and consumption, each control sub-unit 11 may drive a limited number (three or, as in the case illustrated, four) of driving sub-units 12 connected in parallel, so that a considerable occupation of area is required for the integrated implementation of the sole driving-control unit 7. Moreover, it may be required that all the transistors in the circuit are of the high-voltage type to withstand the high voltage values present across their terminals, which, combined with the high requirements of output current, entails the use of transistors of large dimensions (with large thicknesses of the corresponding oxides), and high costs, and once again a considerable occupation of space. Given that the entire driving stage 6 is supplied by the charge-pump stage 10, the latter must be sized so as to meet the high current requirements thereof, and in particular the inefficiency of the driving stage 6 results in a high consumption of current required of the charge-pump stage 10.